1. Field of the Invention
The present invention relates to a semiconductor device such as a base cell (standard cell)-type semi-custom logic semiconductor device.
2. Description of the Related Art
A typical standard cell-type logic semiconductor device includes a plurality of standard cell (logic cell) areas, and a plurality of wiring channel areas therebetween. Within each of the logic cell areas, the widths of logic cells can be different from each other in accordance with the functions thereof, while the heights of the logic cells are the same and definite. Therefore, virtual terminals (which are defined by a computer-aided design (CAD)) of the two adjacent logic cells within each of the logic cell areas are directly connected by a so-called batting method, which is one of the features of the standard cells. Hereinafter, note that virtual terminals are simply referred to as "terminals". On the other hand, the wiring channel areas for connecting the logic cells belonging to the two adjacent logic cell areas to each other are variable, and therefore, an automatic wiring method using a channel router is carried out to enhance the integration of the device.
In the above-mentioned logic cell areas, if opposing edges of two adjacent logic cells do not have the same type terminal arrangement, the two adjacent logic cells cannot be directly connected to each other by the batting method. In this case, even if the two logic cells are separated by a space or a non-logic cell, each of the two logic cells may have terminals which cannot be automatically connected by the-channel router, since the channel router provides wiring only along one direction. This will be explained later in detail.
There are three prior art methods for performing a wiring operation upon the terminals of the specific logic cells which cannot be connected by the channel router.
A first wiring method is carried out manually by using an interactive CRT on which the terminals of the specific logic cells are splayed. In the first wiring method, however, the efficiency of design is decreased, thus increasing the manufacturing cost of the device.
In a second wiring method, logic cell areas having specific logic cells are divided into two rows, so that one specific logic cell belongs to one row and the other specific logic cell belongs to the other row. In the second wiring method however, the device is enlarged, thus reducing the integration of the device. This will be explained later in detail.
In a third wiring method, a wiring cell is provided between the two specific logic cells (see: JP-A-61-114550). Even in the third wiring method, all of the terminals of the specific logic cells are not always connected to each other, this will be explained later in detail.